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HD-15531
March 1997
CMOS Manchester Encoder-Decoder
Description
The Intersil HD-15531 is a high performance CMOS device intended to service the requirements of MIL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate independently of each other, except for the master reset and word length functions. This circuit provides many of the requirements of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recognizes the sync pulse and identifies it as well as decoding the data bits and checking parity. The HD-15531 also surpasses the requirements of MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately. This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 over both temperature and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate. The HD-15531 can also be used in many party line digital data communications applications, such as a local area network or an environmental control system driven from a single twisted pair of fiber optic cable throughout a building.
Features
* Support of MIL-STD-1553 * Data Rate (15531B) . . . . . . . . . . . . . . . 2.5 Megabit/Sec * Data Rate (15531) . . . . . . . . . . . . . . . . 1.25 Megabit/Sec * Variable Frame Length to 32 Bits * Sync Identification and Lock-In * Separate Manchester II Encode, Decode * Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE TEMP. RANGE
PDIP CERDIP -40oC to +85oC
1.25MBIT /SEC -
2.5MBIT /SEC
PKG. NO.
HD3-15531B-9 E40.6 HD1-15531B-9 F40.6 HD1-15531B-8 F40.6 HD1-15531
-40oC to +85oC HD1-15531-9 -55oC to +125oC HD1-15531-8
DESC (CERDIP)
-55oC to +125oC 59629054901MQA -55oC to +125oC 59629054902MQA
F40.6
HD1-15531B
F40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2961.1
5-1
HD-15531 Pinout
HD-15531 (CERDIP, PDIP) TOP VIEW
VCC VALID WORD TAKE DATA' TAKE DATA SERIAL DATA OUT SYNCHR DATA SYNCHR DATA SEL SYNCHR CLK DECODER CLK 1 2 3 4 5 6 7 8 9 40 COUNT C1 39 COUNT C4 38 DATA SYNC 37 ENCODER CLK 36 COUNT C3 35 NC 34 ENCODER SHIFT CLK 33 SEND CLK IN 32 SEND DATA 31 ENCODER PARITY SEL 30 SYNC SEL 29 ENCODER ENABLE 28 SERIAL DATA IN 27 BIPOLAR ONE OUT 26 OUTPUT INHIBIT 25 24 BIPOLAR ZERO OUT
SYNCHR CLK SEL 10 BIPOLAR ZERO IN 11 BIPOLAR ONE IN 12 UNIPOLAR DATA IN 13 DECODER SHIFT CLK 14 TRANSITION SEL 15 NC 16 COMMAND SYNC 17 DECODER PARITY SEL 18 DECODER RESET 19 COUNT C0 20
/ 6 OUT
23 COUNT C2 22 MASTER RESET 21 GND
Block Diagrams
ENDODER
21 22 33 24
GND MASTER RESET SEND CLK IN
VCC OUTPUT INHIBIT
1
/ 6 OUT /2 /6
CHARACTER FORMER 27
26
BIPOLAR ONE OUT BIPOLAR ZERO OUT
25
37
ENCODER CLK
BIT COUNTER 32 20 C0 40 C1 23 C2 36 C3 39 C4 34 28 29 30 31
SEND DATA
SERIAL DATA IN
SYNC SELECT ENCODER PARITY SELECT
ENCODER SHIFT CLK
ENCODER ENABLE
5-2
HD-15531
DECODER
7 8
SYNCHRONOUS DATA SELECT UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ONE IN 13 12 11 TRANSITION FINDER
SYNCHRONOUS DATA 4 TAKE DATA COMMAND SYNC DATA SYNC 5 SERIAL DATA OUT VALID WORD PARITY SELECT DECODER SHIFT CLK
DATA SELECT GATE
CHARACTER IDENTIFIER
17
DECODER CLK DECODER CLK SELECT SYNCHRONOUS CLK SYNCHRONOUS CLK SELECT MASTER RESET
9 15 SYNCHRONIZER 8
CLOCK SELECT DATA
BIT RATE CLK
2 PARITY CHECK 16
14 10 22
DECODER RESET
19
BIT COUNTER 23 C1 C2 36 C3 39 C4
3
TAKE DATA'
20 40 C0
Pin Description
PIN NUMBER 1 2 3 O O TYPE VCC VALID WORD TAKE DATA' NAME SECTION Both Decoder Decoder DESCRIPTION Positive supply pin. A 0.1F decoupling capacitor from VCC (pin 1) to GROUND (pin 21) is recommended. Output high indicates receipt of a valid word, (valid parity and no Manchester errors). A continuous, free running signal provided for host timing or data handling. When data is present on the bus, this signal will be synchronized to the incoming data and will be identical to TAKE DATA. Output is high during receipt of data after identification of a valid sync pulse and two valid Manchester bits. Delivers received data in correct NRZ format. Input presents Manchester data directly to character identification logic. SYNCHRONOUS DATA SELECT must be held high to use this input. If not used, this pin must be held high. In high state allows the synchronous data to enter the character identification logic. Tie this input low for asynchronous data. Input provides externally synchronized clock to the decoder, for use when receiving synchronous data. This input must be tied high when not in use. Input drives the transition finder, and the synchronizer which in turn supplies the clock to the balance of the decoder. Input a frequency equal to 12X the data rate. In high state directs the SYNCHRONOUS CLOCK to control the decoder character identification logic. A low state selects the DECODER CLOCK. A high input should be applied when the bus is in its negative state. This pin must be held high when the unipolar input is used. A high input should be applied when the bus is in its positive state. This pin must he held low when the unipolar input is used. With pin 11 high and pin 12 low, this pin enters unipolar data into the transition finder circuit. If not used this input must be held low.
4 5 6
O O I
TAKE DATA SERIAL DATA OUT SYNCHRONOUS DATA SYNCHRONOUS DATA SELECT SYNCHRONOUS CLOCK DECODER CLOCK SYNCHRONOUS CLOCK SELCT BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN
Decoder Decoder Decoder
7 8 9 10 11 12 13
I I I I I I I
Decoder Decoder Decoder Decoder Decoder Decoder Decoder
5-3
HD-15531 Pin Description
PIN NUMBER 14 15 TYPE O I (Continued)
NAME DECODER SHIFT CLOCK TRANSITION SELECT NC
SECTION Decoder Decoder
DESCRIPTION Output which delivers a frequency (DECODER CLOCK + 1 2), synchronous by the recovered serial data stream. A high input to this pin causes the transition finder to synchronize on every transition of input data. A low input causes the transition finder to synchronize only on mid-bit transitions. Not connected. Output of a high from this pin occurs during output of decoded data which was preceded by a Command (or Status) synchronizing character. An input for parity sense, calling for even parity with input high and odd parity with input low. A high input to this pin during a rising edge of DECODER SHIFT CLOCK resets the decoder bit counting logic to a condition ready for a new word. One of five binary inputs which establish the total bit count to be encoded or decoded. Supply pin. A high on this pin clears 2:1 counters in both encoder and decoder, and resets the / 6 circuit. See pin 20. Output from 6:1 divider which is driven by the ENCODER CLOCK. An active low output designed to drive the zero or negative sense of a bipolar line driver. A low on this pin forces pin 25 and 27 high, the inactive states. An active low output designed to drive the one or positive sense of a bipolar line driver. Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. A high on this pin initiates the encode cycle. (Subject to the preceding cycle being complete). Actuates a Command sync for an input high and Data sync for an input low. Sets transmit parity odd for a high input, even for a low input. Is an active high output which enables the external source of serial data. Clock input at a frequency equal to the data rate X2, usually driven by / 6 output. Output for shifting data into the Encoder. The Encoder samples SDI pin-28 on the low-to-high transition of ESC. Not connected. See pin 20. Input to the 6:1 divider, a frequency equal to 12 times the data rate is usually input here. Output of a high from this pin occurs during output of decoded data which was preceded by a data synchronizing character. See pin 20. See pill 20.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I I O I I I I O O I O I I I I O I O O I I I
Blank Decoder Decoder Decoder Both Both Both Both Encoder Encoder Encoder Encoder Encoder Encoder Encoder Encoder Encoder Encoder Encoder Blank Both Encoder Decoder Both Both
COMMAND SYNC DECODER PARITY SELECT DECODER RESET COUNT C0 GROUND MASTER RESET COUNT C2
/ 6 OUT
BIPOLAR ZERO OUT OUTPUT INHIBIT BIPOLAR ONE OUT SERIAL DATA IN ENCODER ENABLE SYNC SELECT ENCODER PARITY SELECT SEND DATA SEND CLOCK IN ENCODER SHIFT CLOCK NC COUNT C3 ENCODER CLOCK DATA SYNC COUNT C4 COUNT C1
5-4
HD-15531 Encoder Operation
The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SEND CLOCK by dividing the DECODER CLOCK. The frame length is set by programming the COUNT inputs. Parity is selected by programming ENCODER PARITY SELECT high for odd parity or low for even parity. The Encoder's cycle begins when ENCODER ENABLE is high during a falling edge of ENCODER SHIFT CLOCK 1 . This cycle lasts for one word length or K + 4 ENCODER SHIFT CLOCK periods, where K is the number of bits to be sent. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high SYNC SELECT input actuates a Command sync or a low will produce a Data sync for the word 2 . When the Encoder is ready to accept data, the SEND DATA output will go high for K ENCODER SHIFT CLOCK periods 4 . During these K periods the data should
TIMING SEND CLOCK ENCODER SHIFT CLOCK ENCODER ENABLE SYNC SELECT SEND DATA SERIAL DATA IN BIPOLAR ONE OUT BIPOLAR ZERO OUT 1 2
MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 BIT K-5 BIT 4 BIT 3 BIT 2 BIT 1
be clocked into the SERIAL DATA input with every high-tolow transition of the ENCODER SHIFT CLOCK 3 - 4 so it can be sampled on the low-to-high transition. After the sync and Manchester II encoded data are transmitted through the BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder adds on an additional bit with the parity for that word 5 . If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time 5 (as shown) to prevent a consecutive word from being encoded. At any time a low on OUTPUT INHIBIT input will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To abort the Encoder transmission, a positive pulse must be applied at MASTER RESET. Any time after or during this pulse, a low-to-high transition on SEND CLOCK clears the internal counters and initializes the Encoder for a new word.
0
1
2
3
4
5
6
7
N-4
N-3
N-2
N-1
N
DON'T CARE VALID DON'T CARE
1ST HALF 2ND HALF
MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4
BIT 4
BIT 3
BIT 2
BIT 1 PARITY
SYNC
SYNC
MSB
BIT K-1 BIT K-2 BIT K-3 BIT K-4
BIT 4
BIT 3
BIT 2
BIT 1 PARITY
3
4
5
FIGURE 1. ENCODER
Decoder Operation
To operate the Decoder asynchronously requires a single clock with a frequency of 12 times the desired data rate applied at the DECODER CLOCK input. To operate the Decoder synchronously requires a SYNCHRONOUS CLOCK at a frequency 2 times the data rate which is synchronized with the data at every high-to-low transition applied to the SYNCHRONOUS CLK input. The Manchester II coded data can be presented to the Decoder asynchronously in one of two ways. The BIPOLAR ONE and BIPOLAR ZERO inputs will accept data from a comparator sensed transformer coupled bus as specified in Military Spec 1553. The UNIPOLAR DATA input can only accept noninverted Manchester II coded data. (e.g., from BIPOLAR ONE OUT on an Encoder through an inverter to Unipolar Data Input). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized 1 , the type of sync is indicated by a high level at either COMMAND SYNC or DATA SYNC output. If the sync character was a command sync the COMMAND SYNC output will go high 2 and remain high for K SHIFT CLOCK periods 3 , where K is the number of bits to be received. If the sync character was a data sync, the DATA SYNC output will go high. The TAKE DATA output will go high and remain high 2 - 3 while the Decoder is transmit-
5-5
HD-15531
ting the decoded data through SERIAL DATA OUT. The decoded data available at SERIAL DATA OUT is in NRZ format. The DECODER SHIFT CLOCK is provided so that the decoded bits can get shifted into an external register on every low-to-high transition of this clock 2 - 3 . Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. After all K decoded bits have been transmitted 3 the data is checked for parity. A high input on DECODER PARITY SELECT will set the Decoder to check for even parity or a low input will set the Decoder to check for odd parity. A high on VALID WORD output 4 indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately K + 4 DECODER SHIFT CLOCK periods after it goes high, if not reset low sooner by a valid sync and two valid Manchester bits as shown 1 . At any time in the above sequence a high input on DECODER RESET during a low-to-high transition of DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.
TIMING SYNCHRONOUS CLOCK DECODER SHIFT CLOCK BIPOLAR ONE IN BIPOLAR ZERO IN
0
1
2
3
4
5
6
7
8
N-3
N-2
N-1
N
1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 BIT K-5
BIT 3
BIT 2
BIT 1 PARITY
SYNC
SYNC
MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4 BIT K-5
BIT 3
BIT 2
BIT 1 PARITY
TAKE DATA COMMAND SYNC DATA SYNC
SERIAL DATA OUT
UNDEFINED
MSB
BITK-1 BITK-2 BITK-3
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
(MAY BE HIGH FROM PREVIOUS RECEPTION) VALID WORD
1
2
3
4
FIGURE 2. DECODER
5-6
HD-15531 Frame Counter
PIN WORD DATA BITS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NOTE: 1. The above table demonstrates all possible combinations of frame lengths ranging from 6 to 32 bits. The pin word described here is common to both the Encoder and Decoder. FRAME LENGTH (BIT PERIODS) 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 C4 L L L L L L L L L L L H H H H H H H H H H H H H H H H C3 L L L H H H H H H H H L L L L L L L L H H H H H H H H C2 H H H L L L L H H H H L L L L H H H H L L L L H H H H C1 L H H L L H H L L H H L L H H L L H H L L H H L L H H C0 H L H L H L H L H L H L H L H L H L H L H L H L H L H
5-7
HD-15531
VALID WORD
VCC
TAKE DATA
COUNT C1 COUNT C4
SYNC DATA SYNC DATA SELECT SYNC CLOCK DECODER CLOCK SYNC CLOCK SELECT BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN TRANSITION SELECT COMMAND SYNC DECODER PARITY SELECT COUNT C0
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
DATA SYNC NC COUNT C3 ENCODER PARITY SEL. SYNC SELECT ENCODER ENABLE BIPOLAR ONE OUT INHIBIT OUTPUT BIPOLAR ZERO OUT
A
B
CK H
AB 74164
CK
OH SH/LD CK SI 74165
OH SH/LD CK SI 74165 COUNT C2 MASTER RESET
74164
PARALLEL OUT
PARALLEL IN
FIGURE 3. HOW TO MAKE OUR MTU LOOK LIKE A MANCHESTER ENCODED UART
Typical Timing Diagrams for a Manchester Encoded UART
ENCODER ENABLE
SYNC SELECT VALID PARALLEL IN VALID
BIPOLAR ONE OUT
P
BIPOLAR ZERO OUT SYNC MSB LSB
P PARITY
FIGURE 4. ENCODER TIMING
5-8
HD-15531
SYNC BIPOLAR ONE IN MSB LSB PARITY P
BIPOLAR ZERO IN
P
COMMAND SYNC
PARALLEL OUT
VALID
VALID
VALID WORD
FROM PREVIOUS RECEPTION
FIGURE 5. DECODER TIMING
MIL-STD-1553
The 1553 Standard defines a time division multiplexed data bus for application within aircraft. The bus is defined to be bipolar, and encoded in a Manchester II format, so no DC component appears on the bus. This allows transformer coupling and excellent isolation among systems and their environment. The HD-15531 supports the full bipolar configuration, assuming a bus driver configuration similar to that in Figure 1. Bipolar inputs from the bus, like Figure 2, are also accommodated. The signaling format in MIL-STD-1553 is specified on the assumption that the network of 32 or fewer terminals are controlled by a central control unit by means of CommandWords, and Data. Terminals respond with Status Words, and Data. Each word is preceded by a synchronizing pulse, and followed by parity bit, occupying a total of 20s. The word formats are shown in Figure 4. The special abbreviations are as follows: P R/T ME TF Parity, which is defined to be odd, taken across all 17 bits. Receive on logical zero, transmit on ONE. Message Error if logical 1. Terminal Flag, if set, calls for controller to request self-test data.
The paragraphs above are intended only to suggest the content of MIL-STD-1553, and do not completely describe its bus requirements, timing or protocols.
BUS "1" + "1" REF "0" REF "0" + "0" "1"
FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER
FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER
5-9
HD-15531
COMMAND SYNC
DATA SYNC
BIT PERIOD
BIT PERIOD
BIT PERIOD
LOGICAL ONE DATA
LOGICAL ZERO DATA
FIGURE 8. MIL-STD-1553 CHARACTER FORMATS
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16 17
18
19
COMMAND WORD (FROM CONTROLLER TO TERMINAL) 5 SYNC TERMINAL ADDRESS R/T DATA WORD (SENT EITHER DIRECTION) 1 5 SUB ADDRESS /MODE 5 DATA WORD COUNT 1 P
16 SYNC DATA WORD
1
P
STATUS WORD (FROM TERMINAL TO CONTROLLER) 5 SYNC TERMINAL ADDRESS 1 9 CODE FOR FAILURE MODES 1 TF 1 P
FIGURE 9. MIL-STD-1553 WORD FORMATS NOTE: 1. This page is a summary of MIL-STD-1553 and is not intended to describe the operation of the HD-15531.
5-10
HD-15531
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA JC CERDIP Package . . . . . . . . . . . . . . . . . . 35oC/W 9oC/W PDIP Package . . . . . . . . . . . . . . . . . . . . . 50oC/W N/A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) HD-15531-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC HD-15531-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Encoder/Decoder Clock Rise Time (TECR, TDCR) . . . . . . .8ns Max Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . .8ns Max
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates Sync. Transition Span (TD2) . . . . . . . . . . . 18 TDC Typical, (Note 1) Short Data Transition Span (TD4) . . . . . . . . 6 TDC Typical, (Note 1) Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
PARAMETER Input LOW Voltage Input HIGH Voltage Input LOW Clock Voltage Input HIGH Clock Voltage Output LOW Voltage Output HIGH Voltage Input Leakage Current Standby Supply Current
VCC = 5.0V 10%, TA = -40oC to +85Co (HD-15531-9) TA = -55oC to +125Co (HD-15531-8) SYMBOL VIL VIH VILC VIHC VOL VOH II ICCSB ICCOP TEST CONDITIONS VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V VCC = 4.5V and 5.5V IOL = +1.8mA, VCC = 4.5V (Note 2) IOH = -3.0mA, VCC = 4.5V (Note 2) VI = VCC or GND, VCC = 5.5V VIN = VCC = 5.5V, Outputs Open VIN = VCC = 5.5V, f = 15MHz, Outputs Open (Note 3) MIN 0.7 VCC VCC -0.5 2.4 -1.0 MAX 0.2 VCC GND +0.5 0.4 +1.0 2 UNITS V V V V V V A mA
Operating Power Supply Current
-
10
mA
Functional Test NOTES: 1. TDC = Decoder clock period = 1/FDC.
FT
-
-
-
2. Interchanging of force and sense conditions is permitted. 3. Tested as follows: f = 15MHz, VIH = 70% VCC, VIL = 20% VCC, CL = 50pF, VOH VCC/2 and VOL VCC/2.
Capacitance
SYMBOL CIN COUT
TA = +25oC, Frequency = 1MHz PARAMETER Input Capacitance Output Capacitance TYP 25 25 UNITS pF pF TEST CONDITIONS All measurements are referenced to device GND
5-11
HD-15531
AC Electrical Specifications
VCC = 5V 10%, TA = -40oC to +85oC (HD-15530-9) TA = -55oC to +125oC (HD-15530-8) HD-15531 SYMBOL ENCODER TIMING FEC FESC FED TMR TE1 TE2 TE3 TE4 TE5 TE6 TE7 TE8 TE9 TE10 TE11 Encoder Clock Frequency Send Clock Frequency Encoder Data Rate Master Reset Pulse Width Shift Clock Delay Serial Data Setup Serial Data Hold Enable Setup Enable Pulse Width Sync Setup Sync Pulse Width Send Data Delay Bipolar Output Delay Enable Hold Sync Hold 150 75 75 90 100 55 150 0 10 95 15 2.5 1.25 125 50 130 150 50 50 90 100 55 150 0 10 95 30 5.0 2.5 80 50 130 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF PARAMETER MIN MAX HD-15531B MIN MAX UNITS TEST CONDITIONS (NOTE 2)
DECODER TIMING FDC FDS FDD TDR TDRS TDRH TMR TD1 TD3 TD6 TD7 TD8 TD9 TD10 TD11 TD12 TD13 NOTES: 1. TDC = Decoder clock period = 1/FDC. 2. AC Testing as follows: Input levels: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference levels: VCC/2; Output load: CL = 50pF. Decoder Clock Frequency Decoder Sync Clock Decoder Data Rate Decoder Reset Pulse Width Decoder Reset Setup Time Decoder Reset Hold Time Master Reset Pulse Bipolar Data Pulse Width One Zero Overlap Sync Delay (ON) Take Data Delay (ON) Serial Data Out Delay Sync Delay (OFF) Take Data Delay (OFF) Valid Word Delay Sync Clock to Shift Clock Delay Sync Data Setup 150 75 10 150 TDC + 10 (Note 1) -20 0 0 0 0 75 15 2.5 1.25 TDC - 10 (Note 1) 110 110 80 110 110 110 75 150 75 10 150 TDC + 10 (Note 1) -20 0 0 0 0 75 30 5.0 2.5 TDC - 10 (Note 1) 110 110 80 110 110 110 75 MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF VCC = 4.5V and 5.5V, CL = 50pF
5-12
HD-15531 Timing Waveforms
SEND CLOCK TE1 ENCODER SHIFT CLOCK TE2 SERIAL DATA IN VALID TE3 VALID
SEND CLOCK TE1 ENCODER SHIFT CLOCK TE4 TE11 TE10
ENCODER ENABLE SYNC SELECT
TE5
TE6 VALID TE7
ENCODER SHIFT CLOCK TE8 SEND DATA
SEND CLOCK TE9 BIPOLAR ONE OUT OR BIPOLAR ZERO OUT
FIGURE 10. ENCODER TIMING
5-13
HD-15531 Timing Waveforms
(Continued)
NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS. BIT PERIOD BOI
TD1
BIT PERIOD
BIT PERIOD
TD2 BZI COMMAND SYNC
TD3
TD1
TD3
TD2
BOI TD2
TD1
TD1
TD3
TD3
BZI DATA SYNC TD2
BOI BZI
TD1 TD3 TD3 TD2 TD4
TD1 TD3 TD1 TD3 TD3
TD5 ONE ZERO
TD5 ONE
TD4
NOTE: BIPOLAR ONE IN = 0, BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.
UI
TD2 COMMAND SYNC
TD2
UI
TD2 DATA SYNC
TD2
UI
TD4 ONE
TD5 ZERO
TD5 ONE
TD4
TD4 ONE
FIGURE 11. DECODER TIMING
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HD-15531 Timing Waveforms
(Continued)
DECODER SHIFT CLOCK TD6 COMMAND/DATA SYNC TD7 TAKE DATA
DECODER SHIFT CLOCK TD8 SERIAL DATA OUT TD10 DATA BIT
DECODER SHIFT CLOCK TD9 COMMAND/DATA SYNC TD10 TAKE DATA
VALID WORD
TD11
DECODER SHIFT CLOCK TDRS DECODER RESET TDR TDRH
SYNCHRONOUS INPUT (WITH EXTERNAL BIT SYNCHRONIZATION) SYNCHRONOUS CLOCK IN TD12 DECODER SHIFT CLOCK
SYNCHRONOUS CLOCK IN TD13 SYNCHRONOUS DATA IN TD13 MANCHESTER PHASES TD13 TD13
FIGURE 12. DECODER TIMINGS
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HD-15531 Test Load Circuit
DUT INPUT CL (NOTE 1) VIH 50% VIL 50% VOL OUTPUT VOH
AC Testing Input, Output Waveform
FIGURE 13. NOTE: 1. Includes stray and jig capacitance. NOTE:
FIGURE 14.
1. AC Testing: All input signals must switch between VIL and VIH, input rise and fall times are driven at 1ns per volt.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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